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Cypress Semiconductor /psoc63 /SCB0 /RX_FIFO_STATUS

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Interpret as RX_FIFO_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0USED0 (SR_VALID)SR_VALID 0RD_PTR0WR_PTR

Description

Receiver FIFO status

Fields

USED

Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR.
SR_VALID

Indicates whether the RX shift registers holds a (partial) valid data frame (‘1’) or not (‘0’). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).
RD_PTR

FIFO read pointer: FIFO location from which a data frame is read.
WR_PTR

FIFO write pointer: FIFO location at which a new data frame is written by the hardware.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data